Parallelized computation of compressed BEM matrices on multiprocessor computer clusters

Abstract

Purpose

Various parallelization strategies are investigated to mainly reduce the computational costs in the context of boundary element methods and a compressed system matrix.

Design/methodology/approach

Electrostatic field problems are solved numerically by an indirect boundary element method. The fully dense system matrix is compressed by an application of the fast multipole method. Various parallelization techniques such as vectorization, multiple threads, and multiple processes are applied to reduce the computational costs.

Findings

It is shown that in total a good speedup is achieved by a parallelization approach which is relatively easy to implement. Furthermore, a detailed discussion on the influence of problem oriented meshes to the different parts of the method is presented. On the one hand the application of problem oriented meshes leads to relatively small linear systems of equations along with a high accuracy of the solution, but on the other hand the efficiency of parallelization itself is diminished.

Research limitations/implications

The presented parallelization approach has been tested on a small PC cluster only. Additionally, the main focus has been laid on a reduction of computing time.

Practical implications

Typical properties of general static field problems are comprised in the investigated numerical example. Hence, the results and conclusions are rather general.

Originality/value

Implementation details of a parallelization of existing fast and efficient boundary element method solvers are discussed. The presented approach is relatively easy to implement and takes special properties of fast methods in combination with parallelization into account.

Citation

Buchau, A., Hafla, W., Groh, F. and Rucker, W.M. (2005), "Parallelized computation of compressed BEM matrices on multiprocessor computer clusters", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 24 No. 2, pp. 468-479. https://doi.org/10.1108/03321640510586105