TY  - JOUR
AB  - Purpose– This paper aims to address the various issues of board‐level (off‐chip) interconnects testing. A new algorithm based on the boundary scan architecture is developed to test off‐chip interconnect faults. The proposed algorithm can easily diagnose which two interconnects are shorted.Design/methodology/approach– The problems in board‐level interconnects testing are not simple. A new algorithm is developed to rectify some of the problems in existing algorithms. The proposed algorithm to test board‐level interconnect faults is implemented using Verilog on Modelsim software. The output response of each shorting between different wires of different nodes is different, which is the basis of fault detection by the proposed algorithm. The test vectors are generated by the test pattern generator and these test vectors are different for different nodes. This work implements built in self test using boundary scan technique.Findings– The dominant‐1 (wired‐OR, denoted as WOR), dominant‐0 (wired‐AND, denoted as WAND) and stuck‐at faults are tested using the proposed algorithm. The proposed algorithm is also compared with the several algorithms in the literature, i.e. modified counting, walking one's algorithm and others. This paper's results are found to be better than the existing algorithms.Research limitations/implications– The limitation of the proposed algorithm is that, at any time, the faults on any seven nodes can be tested to avoid aliasing. So, the groups are formed out of total nodes, in a multiple of seven to carry out the testing of faults.Practical implications– The proposed algorithm is free from the problems of syndromes and utilizes a smaller number of test vectors.Originality/value– Various existing algorithms namely modified counting, walking one's algorithm and others are discussed. A new algorithm is developed which can easily detect board‐level dominant‐1 (WOR), dominant‐0 (WAND) and stuck‐at faults. The proposed algorithm is completely free from aliasing and confounding syndromes.
VL  - 37
IS  - 3
SN  - 0305-6120
DO  - 10.1108/03056121111155648
UR  - https://doi.org/10.1108/03056121111155648
AU  - Sharma D.K.
AU  - Sharma R.K.
AU  - Kaushik B.K.
AU  - Kumar Pankaj
PY  - 2011
Y1  - 2011/01/01
TI  - Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards
T2  - Circuit World
PB  - Emerald Group Publishing Limited
SP  - 27
EP  - 34
Y2  - 2024/04/25
ER  -