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Micro via filling plating technology for IC substrate applications

Cheng‐Ching Yeh (Rockwood Electrochemicals Asia Ltd, Taiwan, R.O.C)
Kuo‐Hsing Lan (Rockwood Electrochemicals Asia Ltd, Taiwan, R.O.C)
Wei‐Ping Dow (National Yunlin University of Science and Technology)
Jui‐Hsia Hsu (Rockwood Electrochemicals Asia Ltd, Taiwan, R.O.C)
Cliff Lee (Rockwood Electrochemicals Asia Ltd, Taiwan, R.O.C)
Chih‐Hao Hsu (Rockwood Electrochemicals Asia Ltd, Taiwan, R.O.C)
Ken Lee (HannStar Board Corporation)
Jordan Chen (Day Star Technology Corporation)
Philip Lu (Yeti Electronics Co., LTD)

Circuit World

ISSN: 0305-6120

Article publication date: 1 September 2004

Abstract

The trend of electronic products toward lighter, thinner, and faster transmission is challenging the printed circuit board industry to incorporate high density interconnection technology (such as build‐up and semi‐additive processes). Micro stacked via is one technology utilized to produce high‐density structures. Dielectric resin, conductive paste or via plating are usually applied for the filling process. As compared with other filling methods, via filling plating technology has advantages in offering a shorter process and higher reliability. This paper discusses the influence of different equipment design, operating conditions and additives on via filling plating technology.

Keywords

Citation

Yeh, C., Lan, K., Dow, W., Hsu, J., Lee, C., Hsu, C., Lee, K., Chen, J. and Lu, P. (2004), "Micro via filling plating technology for IC substrate applications", Circuit World, Vol. 30 No. 3, pp. 26-32. https://doi.org/10.1108/03056120410520588

Publisher

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Emerald Group Publishing Limited

Copyright © 2004, Emerald Group Publishing Limited